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ltc2911 1 2911f typical application description precision triple supply monitor with power-fail comparator the ltc ? 2911 is a low power, high accuracy triple supply monitor with a power-fail comparator. reset timeout may be selected with an external capacitor or set to an internally generated 200ms. the v1 pin monitors a 3.3v supply. the v2 pin monitors a 5v, 2.5v, 1.8v, 1.2v or adjustable supply. a third adjustable input has a nominal 0.5v threshold allowing a resistive divider to confgure its threshold. all three comparators feature a tight 1.5% threshold accuracy over the entire operating temperature range while a glitch flter ensures reliable reset operation. a spare comparator can be confgured to provide early warning of a low voltage condition. it causes the pfo output to pull low when the voltage of the pfi input falls below 0.5v, allowing the power-fail threshold to be confgured with a resistive divider. a latch feature on the tmr pin allows the rst output to be latched to prevent system resets, simplifying margin testing. features applications n ultralow voltage reset: v cc = 0.5v guaranteed n monitors three inputs simultaneously: 3.3v, 5v, adj (ltc2911-1) 3.3v, 2.5v, adj (ltc2911-2) 3.3v, 1.8v, adj (ltc2911-3) 3.3v, 1.2v, adj (ltc2911-4) 3.3v, adj, adj (ltc2911-5) n 1.5% threshold accuracy n power-fail monitor n rst state can be held for margining n low supply current: 30a typical n input glitch immunity n adjustable reset timeout period n selectable internal timeout saves components n space saving 8-lead tsot-23 and 3mm 2mm dfn packages n network servers n desktop and notebook computers n automotive and industrial electronics rst output voltage with 10k pull-up to v1 + ltc2911-2 76.8k 10k 3.3v 2.5v 1.0v 100k 576k li-ion battery stack 100k v1 tmr v2 adj reset lobat rst pfo pfi t rst = 200ms 2911 ta01a gnd system logic dc/dc converter l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6949965, 7292076. v1 (v) 0 v rst (v) 2 4 6 1 3 5 0.5 1.5 2.5 3.5 2911 ta01b 5.5 0 1 2 3 4 4.5 5 v1 = v2
ltc2911 2 2911f supply voltages v1, v2 ................................................... C0.3v to 6.5v input voltages adj ....................................................... C0.3v to 6.5v pfi ........................................................... C0.3v to 2v tmr ............................................ C0.3v to (v1 + 0.3v) output voltages rst, pfo .............................................. C0.3v to 6.5v order information absolute maximum ratings pfi 1 adj 2 tmr 3 gnd 4 8 v2 7 v1 6 pfo 5 rst top view ts8 package 8-lead plastic tsot-23 t jmax = 150c, ja = 195c/w top view 9 gnd ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1v2 v1 pfo rst pfi adj tmr gnd t jmax = 150c, ja = 76c/w exposed pad (pin 9) is gnd, pcb connection optional pin configuration (notes 1, 2, 3) operating temperature range ltc2911c ................................................ 0c to 70c ltc2911i .............................................. C40c to 85c ltc2911h .......................................... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) tsot-23 ............................................................ 300c ltc2911 c ddb C1 #trm pbf lead free designator pbf = lead free finish parts none = lead based finish parts tape and reel #tr = tape and reel #trm = 500-piece tape and reel product selection C1, C2, C3, C4, C5 see product selection guide for details package type ddb = 8-lead (3mm 2mm) plastic dfn ts8 = 8-lead plastic tsot-23 temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C40c to 125c) product part number consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2911 3 2911f product selection guide part number part marking package description v1 v2 ltc2911-1 lfhz 8-lead (3mm 2mm) plastic dfn 3.3v 5v ltc2911-2 lfpg 8-lead (3mm 2mm) plastic dfn 3.3v 2.5v ltc2911-3 lfpj 8-lead (3mm 2mm) plastic dfn 3.3v 1.8v ltc2911-4 lfpm 8-lead (3mm 2mm) plastic dfn 3.3v 1.2v ltc2911-5 lfpp 8-lead (3mm 2mm) plastic dfn 3.3v adj ltc2911-1 ltfjb 8-lead plastic tsot-23 3.3v 5v ltc2911-2 ltfph 8-lead plastic tsot-23 3.3v 2.5v ltc2911-3 ltfpk 8-lead plastic tsot-23 3.3v 1.8v ltc2911-4 ltfpn 8-lead plastic tsot-23 3.3v 1.2v ltc2911-5 ltfpq 8-lead plastic tsot-23 3.3v adj electrical characteristics symbol parameter conditions min typ max units v rt33 3.3v, 5% reset threshold v1 input l 3.036 3.086 3.135 v v rt50 5v, 5% reset threshold v2 input (ltc2911-1) l 4.600 4.675 4.750 v v rt25 2.5v, 5% reset threshold v2 input (ltc2911-2) l 2.300 2.338 2.375 v v rt18 1.8v, 5% reset threshold v2 input (ltc2911-3) l 1.656 1.683 1.710 v v rt12 1.2v, 5% reset threshold v2 input (ltc2911-4) l 1.104 1.122 1.140 v v rta adj pin threshold adj input and v2 input of ltc2911-5 l 492.5 500 507.5 mv v pft pfi pin threshold pfi input threshold (falling) l 492.5 500 507.5 mv ?v pft pfi hysteresis l 10 15 19 mv v cc,op minimum operating voltage to guarantee pfo high (note 3) v pfi = 0.55v l 2.3 v i v1 v1 input current (note 4) v1 = 3.3v, v1 > v2 l 10 30 80 a v1 = 3.3v, v1 < v2 l 3 10 30 a i v2 v2 input current (note 4) v2 = 5v (ltc2911-1) v2 = 2.5v (ltc2911-2) v2 = 1.8v (ltc2911-3) v2 = 1.2v (ltc2911-4) v2 = 0.55v (ltc2911-5) c-grade/i-grade h-grade l l l l l l 10 3 2 2 35 10 10 10 80 30 30 30 15 40 a a a a na na i adj adj input current v adj = 0.55v (c-grade) (i-grade) v adj = 0.55v (h-grade) l l 15 40 na na i pfi pfi input current v pfi = 0.55v (c-grade) (i-grade) v pfi = 0.55v (h-grade) l l 15 40 na na i tmr(up) tmr pull-up current v tmr = 1v l C1.5 C2.2 C2.9 a i tmr(down) tmr pull-down current v tmr = 1v l 1.5 2.2 2.9 a i pu rst, pfo pull-up current v pin = 0v l C20 C29 C40 a the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v adj = 0.55v, v pfi = 0.55v, v1 = 3.3v unless otherwise noted. (notes 2, 3)
ltc2911 4 2911f electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v adj = 0.55v, v pfi = 0.55v, v1 = 3.3v unless otherwise noted. (notes 2, 3) symbol parameter conditions min typ max units t p,pf pfi comparator propagation delay to pfo v pfi driven beyond threshold v pft by more than 10% l 8 30 80 s t uv v1, v2, adj undervoltage detect to rst low v x less than threshold v rtx by more than 10% l 8 30 80 s v oh rst, pfo output voltage high (note 5) i rst = C1a l v1 C 1 v1 v v ol rst, pfo output voltage low (note 6) v cc = 0.5v, i = 5a v cc = 1v, i = 100a v cc = 3v, i = 2.5ma l l l 0.01 0.01 0.10 0.15 0.15 0.30 v v v t rst(ext) reset timeout period, external c tmr = 2.2nf l 15 20 27 ms t rst(int) reset timeout period, internal v tmr = v1 l 140 200 280 ms v tmr(int) timer internal mode threshold v tmr rising l v1 C 0.40 v1 C 0.020 v1 C 0.10 v ?v tmr(int) timer internal mode hysteresis v tmr falling l 40 100 160 mv v tmr(latch) timer latch mode threshold v tmr falling l 0.10 0.20 0.40 v ?v tmr(latch) timer latch mode hysteresis v tmr rising l 40 75 160 mv t p, lr latch release propagation delay to rst low v tmr rising, step 0v to 0.6v l 0.5 3 s t su,mon monitor input setup time to latch enable (note 7) monitor input setup time to latch release v tmr falling, step 0.6v to 0v v tmr rising, step 0v to 0.6v l 2 ms t hd, mon monitor input hold time to latch enable monitor input hold time to latch release v tmr falling, step 0.6v to 0v v tmr rising, step 0v to 0.6v l 0 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: the internal supply voltage (v cc ) is generated from the greater of the voltages on the v1 and v2 inputs. v cc = v1 for the ltc2911-5. note 4: under typical operating conditions, quiescent current is drawn from the greater of the voltages on the v1 and v2 inputs. for the ltc2911 - 5 only v1 supplies the quiescent current. note 5: the rst and pfo output pins on the ltc2911 have internal pull- ups to v1. however, for faster rise times or for v oh voltages greater than v1, use an external pull-up resistor. note 6: the rst and pfo pull-down currents are derived from v1 and v2 except for the ltc2911-5 where the pull-down strength is derived only from v1. note 7: t su,mon is required to latch a low rst state and t su,mon + t rst is required to latch a high rst state.
ltc2911 5 2911f typical performance characteristics pfi hysteresis vs temperature reset timeout period vs temperature rst, pfo voltage output low vs sink current rst, pfo voltage output high vs source current rst, pfo voltage output high vs v cc rst, pfo pin source current vs v1 normalized reset and power-fail threshold voltages vs temperature quiescent supply current vs temperature allowable glitch duration vs overdrive temperature (c) ?50 0.985 normalized threshold voltage (v/v) 0.990 0.995 1.000 1.005 0 50 100 125 2911 g01 1.010 1.015 ?25 25 75 temperature (c) ?50 0 quiescent supply current (a) 10 20 30 40 0 50 100 125 2911 g02 50 60 ?25 25 75 i v2 for ltc2911-1 overdrive (%) 0.1 0 glitch duration (s) 300 400 500 1 10 100 2911 g03 200 100 t amb (c) ?50 hysteresis (mv) 16.0 17.0 125 2911 g04 15.0 14.0 0 50 100 ?25 25 75 18.0 15.5 16.5 14.5 17.5 temperature (c) ?50 140 timeout period (ms) 160 180 200 220 0 50 100 125 2911 g05 240 260 ?25 25 75 internal external c tmr = 22nf sink current (ma) 0 0 voltage output low (v) 0.2 0.4 0.6 0.8 1.0 5 10 15 20 2911 g06 25 30 ?40c 25c 85c 125c 150c v cc = 3v source current (a) 0 voltage output high (v) 2.0 2.5 3.0 15 25 2911 g07 1.5 1.0 5 10 20 30 35 0.5 0 v1 = 3.135v, v2 = 5v for rst v cc (v) 0 ?1 voltage output high (v) 0 2 3 4 6 0.5 2.5 3.5 2911 g08 1 5 2 4.5 5.55 1 1.5 3 4 v1 = v2 = adj = pfi 10k pull-up to v cc rst for ltc2911-1 rst for ltc2911-2 ltc2911-3 ltc2911-4 ltc2911-5 pfo v1 (v) output source current (a) 60 80 100 2911 g09 40 20 0 10 5 6 2 3 4 rst pfo
ltc2911 6 2911f pin functions adj: adjustable voltage monitor input. input to a voltage monitor comparator with a 0.5v nominal threshold. tie to v1 if unused. exposed pad (dfn only): exposed pad may be left open or connected to device ground. gnd: device ground. pfi: power-fail voltage monitor input. input to the power- fail comparator with a 500mv threshold at the falling edge and a 515mv threshold at the rising edge, giving a 3% hysteresis for noise rejection. tie to v1 or gnd if unused. pfo: power-fail logic output. this pin asserts low when the pfi input voltage is below its threshold and goes high when the pfi input voltage is above its threshold. this pin provides a weak pull-up current to v1. this current is typi - cally 29a at v1 = 3.3v. the pin can be pulled to voltages higher than v1 by external pull-up resistors. pfo provides an early warning signal of a system power failure. rst: reset logic output. this pin asserts low when any of the v1, v2, or adj inputs are below their reset thresh - olds. pulls high when all the monitored inputs are above their thresholds for longer than a timeout period. this pin provides a weak pull-up current to v1. this current is typi - cally 29a at v1 = 3.3v. the pin can be pulled to voltages higher than v1 by external pull-up resistors. the status of rst can be latched by holding the tmr pin at gnd. tmr: reset timeout control. attach an external capacitor, c tmr , to gnd to set a reset timeout period of 9.4ms/nf. a low leakage ceramic capacitor is recommended for timer accuracy. a 2.2nf capacitor generates a 20ms timeout. leaving the tmr pin open without a capacitor generates a minimum timeout of approximately 400s which will vary depending on the parasitic capacitance on the pin. tying this pin to v1 enables the internal 200ms timeout. pulling this pin to gnd latches the reset state. v1: 3.3v monitor and power supply input. v1 is an accu - rate 3.3v, C5% undervoltage supply monitor. the internal v cc is generated from the greater of the voltages at the v1 and v2 inputs for the ltc2911-1/ltc2911 - 2/ltc2911- 3/ltc2911-4 options. the ltc2911-5 option always derives its power supply from the v1 pin. bypass this pin to gnd with a 0.1f (or greater) capacitor for the ltc2911-2 through ltc2911-5. v2: voltage monitor and power supply input. v2 is a C5% undervoltage supply monitor for a 5v, 2.5v, 1.8v or 1.2v supply for the ltc2911-1/ltc2911 - 2/ltc2911- 3/ltc2911 - 4 options, respectively. because the internal v cc is generated from the greater of the v1 and v2 inputs for these options, the v2 pin should be bypassed to gnd with a 0.1f (or greater) capacitor for the ltc2911-1. the v2 pin of the ltc2911-5 is a high impedance input with a 0.5v threshold, allowing the trip threshold of the monitored supply to be confgured with a resistive divider.
ltc2911 7 2911f block diagram ? + v2 comp ? + adj comp adj *for options ltc2911-1 through ltc2911-4 only. **omit the resistive divider for the ltc2911-5. 0.5v v2 1.36m r x ** 231k** 263k v1 pfi pfo ? + v1 comp ? + pfi comp adjustable pulse generator low voltage pull-down 200ms pulse generator latch v cc gnd 2911 bd v cc v1 v cc 114k 114k v2* v1 tmr rst low voltage pull-down power detect v1 three-state decode ltc2911 monitored voltages ltc2911-1 ltc2911-2 ltc2911-3 ltc2911-4 ltc2911-5 v2 r x 5v 1.93m 2.5v 850k 1.8v 547k 1.2v 288k adj ** + ?
ltc2911 8 2911f timing diagrams input valid to latch enable setup and hold timing t rst v tmr(latch) v tmr(latch) + ?v tmr(latch) 2911 td04 t > t su,mon 1v rst adj, v1, v2 tmr v rtx t su,mon t hd,mon latch in note: for the ltc2911-5, v1 low resets rst to a low state ?3% overdrive input returning to above v rtx for t > t su,mon , rst pin stays high 3% overdrive margining power up input valid to latch release setup timing input invalid to latch enable setup and hold timing input invalid to latch release setup timing tmr rst adj, v1, v2 t su,mon t uv t hd,mon latch in note: for the ltc2911-5, v1 low resets rst to a low state v tmr(latch) v rtx 1v v tmr(latch) + ?v tmr(latch) t > t su,mon v rtx ?3% overdrive 2911 td05 ?3% overdrive 3% overdrive margining input returning to below v rtx for t > t su,mon , rst pin stays low undervoltage and reset timing latch release to rst low timing v rtx t uv t rst 1.0v 2911 td01 v x rst rst tmr 0.4v 1.0v 2911 td02 note: adj forced low before tmr release t p,lr power-fail timing pfi v pft t p,pf t p,pf 1.0v 2911 td03 pfo latching rst high latching rst low
ltc2911 9 2911f applications information the ltc2911 is a low power, high accuracy triple supply monitor with power-fail comparator. for the ltc2911-1, ltc2911-2, ltc2911-3 and ltc2911 - 4 options, the v1 and v2 pins monitor two supplies. their thresholds are preset internally based on the option chosen. a resistive divider connected to the adj pin confgures the third threshold. for the ltc2911-5, the v2 pin is a high imped - ance adjustable input similar to the adj pin. reset timeout of the device may be selected with an external capacitor or set to an internally generated 200ms. the adj, v1 and v2 inputs must be valid (above their thresholds) for longer than the reset timeout period before the rst pin transitions high. the power-fail comparator causes the pfo pin to pull low when the pfi pin falls below 0.5v. a resistive divider connected to the pfi pin confgures the threshold of the monitored voltage. the pfo output typically provides an early warning of imminent power failure so that the system may begin shutdown procedures such as supply sequencing and/or storage of system state in nonvolatile memory. power-up the ltc2911-1, ltc2911-2, ltc2911-3 and ltc2911-4 supervisors are powered from the v1 and v2 pins, auto - matically selecting the pin with the higher potential. the exception in the device family, the ltc2911-5, derives its internal supply voltage (v cc ) only from v1. when all monitor inputs are above their thresholds, the quiescent supply current drawn from v cc is typically 30a (35a for the ltc2911-1). when the three monitor inputs (v1, v2 and adj) rise above their thresholds, the appropriate timeout delay begins, after which rst pulls to v1. once the pfi input rises above 515mv, the pfo output signals high indicating that the supply or voltage monitored by pfi is above threshold. the ltc2911 uses proprietary low voltage drive circuitry for the rst and pfo pins which holds them low with v cc (the higher of v1 and v2) as low as 0.5v. this helps prevent indeterminate voltages from appearing on the outputs during power-up. for additional details refer to the output pin characteristics section. when v1 and v2 are ramped simultaneously (for ltc2911 - 1/ltc2911-2/ltc2911-3/ltc2911-4), the pull- down current from the rst and pfo pins is about twice the current available when v1 or v2 is grounded. power down on power-down, when the voltage monitored by the power- fail comparator falls below the threshold confgured by its resistive divider, the pfo pin pulls low to provide an early warning of imminent power failure. in a typically confg - ured system, this occurs before the supplies monitored by v1, v2 or adj fall below their thresholds and cause the rst pin to pull low. the rst and pfo pins maintain a logic low output for v cc as low as 0.5v. see the output pin characteristics section for additional details. power-fail monitoring and pfo signaling the ltc2911s pfi input monitors a voltage through a resistive divider and compares it to the internal power-fail threshold. when pfi drops below 0.50v (the power-fail threshold) the pfo output pulls low to provide an early warning of a low voltage condition. when the pfi pin rises above 0.515v again, the pfo output signals high indicating a valid supply condition. the pfi input typically monitors the primary power supply of a system. for example, the pfi pin may monitor the input supply of a dc/dc converter or a li-ion battery stack voltage. the pfo output typically provides a warning to the system that the power supply is on the verge of fail - ing so that it can prepare for a controlled shutdown. for
ltc2911 10 2911f applications information example, the pfo pin may connect to a processor non - maskable interrupt. when the battery pack voltage drops below the shutdown threshold, as sensed at pfi, the pfo pin pulls low to issue an interrupt. next, the processor begins shutdown procedures which may include supply sequencing and/or storage/erasure of system state in nonvolatile memory. threshold accuracy specifying the minimum supply voltage for a system requires the designer to consider three factors: minimum supply voltage for proper operation, power supply toler - ance, and supervisor reset threshold accuracy. highly accurate supervisors ease the design challenge by de - creasing the overall voltage margin required for reliable system operation. the reset threshold band and the power supply tolerance bands should not overlap. this prevents false or nuisance resets when the power supply is actually within its specifed tolerance band. the actual reset threshold of supervisors varies over a specifed band. the ltc2911 supervisor varies 1.5% around its nominal threshold voltage over temperature. figure 1 illustrates a typical 3.3v monitor. the ltc2911 has 1.5% reset threshold accuracy. the nearest practical supervisor trip point is the sum of power supply toler - ance and the ltc2911 tolerance. so a 5% threshold is typically set to C6.5%, excluding resistor errors. thus for a 3.3v 5% threshold, the practical supervisor trip point is at 3.086v. the threshold is guaranteed to lie in the band between 3.036v and 3.135v over the operating temperature range. this 3.135v maximum threshold is at the lower limit of supply tolerance (3.3v C 5%) to prevent false tripping. the system must operate reliably a little below 3.036v (or 3.3v, C8%), or risk malfunction before a reset signal is properly issued. a less accurate supervisor increases the supply voltage tolerance requirements and the risk of system malfunction. the ltc2911s 1.5% threshold voltage specifcation minimizes these requirements. v1 and v2 supply monitors all the ltc2911 options have a v1 threshold equal to 3.086v (3.3v C 6.5%). the v2 thresholds are 4.675v (5v C 6.5%), 2.338v (2.5v C 6.5%), 1.683v (1.8v C 6.5%) and 1.122v (1.2v C 6.5%) for options ltc2911-1, 3.3v 3.135v 1.5% threshold band 3.086v 3.036v region of potential malfunction ?5% supply tolerance ideal supervisor threshold minimum reliable system voltage nominal supply voltage ?6.5% ?8% 2911 f01 figure 1. 1.5% threshold accuracy improves system reliability
ltc2911 11 2911f ltc2911 - 2, ltc2911-3 and ltc2911-4 respectively. v2 of the ltc2911 - 5 option is a high impedance input with a nominal 0.5v threshold. input noise filtering for rst the v1, v2 and adj comparators have a response time that is inversely proportional to overdrive. this characteristic is illustrated in the typical performance characteristics as the graph allowable glitch duration versus overdrive. the adj and the ltc2911-5s v2 pin may be bypassed with a capacitor to increase the fltering in applications that demand it. the resultant rc lowpass flter at the inputs will further reject high frequency components, at the cost of slowing the monitors response to fault conditions. resistor selection for adj the threshold of the supply monitored by the adj pin is confgured with an external resistive divider (r2 and r1) connected between the supply and ground. the tap point for the divider is connected to the adjustable input (adj) which has a 0.5v threshold. (see figure 2) normally, the user selects a trip voltage based on the sup - ply and acceptable tolerances, and a value of r1 based on current drawn. for a given current, i, r1 is given by: r1 = 0.5v i to minimize errors arising from the adj input bias current, a value of less than 100k is recommended for r1. r2 is then chosen by: r2 = r1 ? v trip_ adj 0.5v ? 1 ? ? ? ? ? ? where, v trip_adj is the supply threshold when the adj pin falls below its 0.5v threshold. for accurate monitoring, the resistor tolerance should be as small as possible. resistor tolerance of 0.1% or some trimming of components should be considered for r2/r1 in applications that require an accurate trip point. resistor selection for pfi an external resistive divider (r3 and r4) connected between the supply and ground confgures the threshold of the supply monitored by the power-fail comparator. the tap point for the divider is connected to the pfi input which has a 0.5v threshold. (see figure 3a) resistor selection follows a process similar to that for the adj pin. r3 is given by: r3 = 0.5v i applications information ? + + ? 0.5v 2911 f02 adj ltc2911 r2 r1 v trip figure 2. setting the adjustable (adj) trip point
ltc2911 12 2911f again, to minimize errors arising from the pfi input bias current, a value of less than 100k is recommended for r3. r4 can be chosen either using the pfi falling threshold or the pfi rising threshold. for the falling edge threshold, use the equation: r4 = r3 ? v trip_ pfi_ fall 0.5v ? 1 ? ? ? ? ? ? alternatively, for the rising edge threshold, use the equation: r4 = r3 ? v trip_ pfi_ rise 0.515v ? 1 ? ? ? ? ? ? where v trip_pfi_fall is the supply threshold when the pfi pin falls below the 0.5v falling threshold, and v trip_pfi_rise is the supply threshold when the pfi pin rises above the 0.515v rising threshold. note that v trip_pfi_rise is typically 3% above the v trip_pfi_fall due to the fact that the pfi 515mv rising threshold is 3% above its 500mv falling threshold. in applications that require an accurate trip point, the r4 and r3 resistors should have small tolerances. hysteresis for power-fail comparator the power-fail comparator uses a positive 3% accurate hysteresis to combat spurious triggering while maintain - ing accurate thresholds for both the rising and falling edges. the nominal threshold is 500mv at the falling edge and 515mv at the rising edge. the hysteresis prevents oscillation when the monitored voltage passes through the thresholds. if the pfi pin is connected to an external resistive divider, it may be bypassed with a capacitor for additional noise fltering. increasing the power-fail hysteresis the power-fail comparator hysteresis can be increased by adding two resistors, r5 and r6, as shown in figure 3b. when pfo is low, r5 sinks current from the center tap of the r3 and r4 resistive divider. the upper threshold is therefore given by: v h = 0.515v 1 + r4 r3 + r4 r5 ? ? ? ? ? ? when pfo is high, the series combination of r5 and r6 sources current into the center tap of the r3 and r4 resis - tive divider. this leads to a lower threshold of: v l = 0.5v 1 + r4 r3 ? ? ? ? ? ? ? 3.3v ? 0.5v ( ) r4 r5 + r6 the addition of r5 and r6 increases the hysteresis to: v hyst = v h ? v l = 0.015 1 + r4 r3 ? ? ? ? ? ? + 0.515 r4 r5 ? ? ? ? ? ? + 3.3v ? 0.5v ( ) r4 r5 + r6 applications information figure 3a. setting the power-fail (pfi) trip point ? + + ? 0.5v 2911 f03a pfi v1 114k pfo ltc2911 r4 r3 v trip figure 3b. increasing power-fail hysteresis ? + + ? 0.5v 2911 f03b pfi v1 v1 pfo ltc2911 r4 r6 r5 r3 v trip 114k
ltc2911 13 2911f resistor selection for combined reset and power-fail divider when the power-fail and reset signals are based on the same supply, the pfi and adj inputs may be connected to a single resistive divider formed from three resistors. the confguration is shown in figure 4. for a given bias current i, r a , r b and r c can be calculated from: r a = 0.5v i r b = r a ? v trip_ pfi_ fall v trip _ adj ? 1 ? ? ? ? ? ? r c = r a ? v trip_ adj 0.5v ? 1 ? ? ? ? ? ? ? v trip_ pfi_ fall v trip_ adj ? ? ? ? ? ? for example, consider monitoring a 5v, 5% supply with v trip_pfi_fall = 4.5v and v trip_adj = 4v. the resulting v trip_pfi_rise is equal to 4.63v or 3% above v trip_pfi_fall . the maximum v trip_pfi_rise should not overlap the mini - mum power supply voltage level for pfo to deassert when the supply recovers. mathematically, after factoring in the sum of the power supply tolerance and the ltc2911 toler - ance, the v trip_pfi_rise should be lower than 5v C 6.5%. applications information see threshold accuracy section for more details. in the design, if we wish to consume about 5a in the divider, r a = 100k. we then fnd r b = 12.4k and r c = 787k (nearest 1% standard values). setting the reset timeout rst goes high after the v1, v2 and adj inputs are above their thresholds for a reset timeout period. connecting the tmr pin to v1 enables the internal 200ms timer. to confgure a different reset timeout period connect a capacitor between the tmr pin and ground. the following formula approximates the value of capacitor needed for a particular timeout: c tmr = t rst ? 106.5 [pf/ms] leaving the tmr pin open with no external capacitor generates a reset timeout of approximately 400s. larger capacitors may be used to increase the timeout, but the capacitor leakage current must not exceed 500na. other - wise, the timer accuracy will be severely affected. suitable values of c tmr for a given t rst may be selected from figure 5. ? + ? + + ? 0.5v 2911 f04 pfi adj ltc2911 r b r c r a v trip figure 4. combining pfi/adj monitoring of one supply with three resistors figure 5. external timeout vs c tmr c tmr (f) 10p 0.1 external timeout, t rst (ms) 10 10000 100p 1n 10n 100n 1 2911 f05 1 100 1000
ltc2911 14 2911f applications information reset latch mode at any time, the tmr pin can be pulled low to latch the rst pin status, overriding the reset operation. this feature is useful when testing a system at supply voltages that might otherwise cause the rst pin to assert. if the rst pin is unasserted (high) before the latch is enabled (by pulling the tmr pin low), rst will remain unasserted after the tmr pin is released. this is true provided that all reset monitor inputs are valid when tmr releases, regardless of their state while the tmr pin was low. however, if rst was unasserted before tmr was pulled low, and now one of the inputs is invalid when tmr is released, rst will assert after a t pl,lr propagation delay (see figure 6a). conversely, if rst was asserted (low) latch release tmr adj, v1, v2 t > t su,mon v tmr(latch) v rtx v tmr(latch) + ?v tmr 1.0v 2911 f06a t p,lr rst figure 6a. input toggled low while timer latched. rst goes low t p,lr after latch release tmr latch release v rtx 1.0v 2911 f06b t > t su,mon t rst adj, v1, v2 rst v tmr(latch) v tmr(latch) + ?v tmr figure 6b. input toggled high while timer latched. rst goes high t rst after latch release tmr t rst 1.0v 2911 f06c t < t rst v trm(latch) v rtx rst adj, v1, v2 latch release v tmr(latch) + ?v tmr figure 6c. timer latched before timeout. after latch release, rst stays low for a full timeout before going high tmr v trx 1.0v t > t hd,mon t > t su,mon 2911 f06d no recounting t rst t > t rst adj, v1, v2 rst v trm(latch) latch release margining v tmr(latch) + ?v tmr figure 6d. timer latched after timeout and rst high. rst stays high after margining if inputs are restored before release before tmr was pulled low, and all inputs are valid when tmr is released, rst will deassert (go high) after a t rst delay (see figures 6b and 6c). the rst pin remains as - serted for a full t rst timeout after the tmr pin is released, regardless of the state of the t rst timer before the latch was enabled. the reset latch mode is useful for perform - ing supply margining tests without resetting the system (see figure 6d). at least 2.9a of pull-up or pull-down current is required to hold the tmr pin high or low to confgure the internal timer or reset latch mode. however, during the timer mode transition, 100a will be required to switch the tmr foat - ing state to ground or v1. connecting the tmr pin to any voltage other than ground or v1 may have unpredictable results.
ltc2911 15 2911f output pin characteristics the dc characteristics of the rst and pfo pull-down strength are shown in the typical performance character - istics. the circuits that drive the pull-down of the output pins are powered by the internal v cc (the greater voltage of v1 or v2). during power-up, a v cc of at least 0.5v en - sures a low output state. the v ol voltage depends on the current sunk by rst and pfo as shown in the figure 8. the open-drain nature of the rst and pfo pins allows for wire-ored connections. for example, multiple ltc2911s may be wire-ored to monitor additional supplies, or open- drain logic can be connected to allow other conditions to issue the reset and/or power-fail signals. output pin rise and fall time the open-drain output pins (rst and pfo) contain weak pull-up circuitry to v1. use an external pull-up resistor when the outputs need to pull beyond v1 and/or require a faster rise time. use external pull-up resistor values of 100k or less. when output pins are externally pulled up to voltages higher than v1, an internal network automatically protects the weak pull-up circuitry from reverse currents. for a given external load capacitance or c load , the rise and fall times can be estimated using figure 9. the output pins have very strong pull-down capability. with a 150pf load capacitance the reset line can pull down in about 30ns. during power-up, with a capacitor connected to the tmr pin, the part remains in the reset latch mode described above until the 2.2a fowing out of the tmr pin charges the capacitor beyond the v tmr(latch) threshold. for this reason, large capacitors will extend the rst timeout during power-up. for example, if c tmr = 1f, the ltc2911 leaves the reset latch mode 90ms after power-up and the rst pin goes high after a 9 second timeout. figures 7a and 7b show how the tmr pin can be driven low to latch the state of the rst pin or foated or driven high for external and internal reset timing, respectively. tmr 2911 f07a system logic tmr v1 2911 f07b system logic figure 7a. open-drain (or three-state buffer) output. grounds tmr to latch the state of rst. floats tmr for external reset timing figure 7b. v1 powered inverter. grounds tmr to latch the state of rst. drives tmr high for internal reset timing applications information i sink (a) 0 voltage output low (mv) 1200 1600 2000 80 2911 f08 800 400 0 2010 4030 60 70 90 50 100 v cc = 0.5v figure 8. voltage output low vs i sink at v cc = 0.5v c load (f) 10n t fall or t rise (s) 1 100 100n 10 1m 10m 100p 1n 10n 2911 f09 1n 10p t rise ltc2911-1 t fall ltc2911-1 figure 9. t rise and t fall vs c load
ltc2911 16 2911f typical applications triple supply monitor and overtemperature signal ltc2911-1 r1 100k r3 270k *thermistor murata ntc ncp15wm474j03rc tolerance 5%. ntc resistance is 474k at room, 35.8k at 85c **optional bypass capacitor for supply transient noise filtering r2 2.05m r31* r4 200k v trip = 10.75v v1 v2 3.3v 5v 12v 3.3v 5v 12v pfi reset overtemp rst pfo tmr adj c tmr 2.2nf t rst = 20ms trip temperature = 90c recover temperature = 89c c1** 10nf 0.1f 2911 ta02 gnd quad supply monitor ltc2911-2 r3 100k r1 100k d1 bas119 r6 383k r4 806k 3.3v 2.5v 5v 12v v trip = 4.53v v trip = 10.5v r5 1.62m v1 v2 pfi reset rst pfo tmr adj c tmr 2.2nf t rst = 20ms 0.1f 2911 ta03 gnd
ltc2911 17 2911f 48v telecom uv/ov monitor with hysteresis ltc2911-1 v1 v2 adj ov 2911 ta04 5v uv 5.6v m1 r pu1 10k r cc 27k 0.25w 0.1f 16v rst pfo tmr pfi gnd r3 13.7k m1: fdg6301n or similar v uv(rising) = 43.3v v uv(falling) = 38.7v v ov(rising) = 70.8v v ov(falling) = 68.8v r4 1.87m r1 18.7k r2b 169k r2a 1.43m v in 36v to 72v typical applications 4-cell nimh stack voltage monitor with input overvoltage signaling ltc2911-2 v1 v2 adj ov t rst = 200ms 0.1f 2911 ta05 lobat rst pfo tmr pfi gnd r3 102k battery low reset threshold = 3.38v overvoltage trip threshold = 6.47v overvoltage recover threshold = 6.28v r4 1.18m r1 100k r2 576k 1.2v 1n5817 1.2v 1.2v 1.2v from charger + + + + 4-cell alkaline stack voltage monitor with early power-fail warning ltc2911-2 v1 v2 adj lobat 0.1f t rst = 200ms 2911 ta06 reset rst pfo tmr pfi gnd r a 100k power-fail falling threshold = 3.90v power-fail rising threshold = 4.02v reset threshold = 3.39v r c 665k r b 15k 1.5v 1.5v 1.5v 1.5v + + + +
ltc2911 18 2911f package description ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc2911 19 2911f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc
ltc2911 20 2911f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0910 ? printed in usa related parts typical application part number description comments ltc1326/ltc1326-2.5 micropower precision triple supply monitor for 5v/2.5v, 3.3v and adj 4.725v, 3.118v, 1v threshold (0.75%) ltc1536 precision triple supply monitor for pci applications meets pci t fail timing specifcations ltc1726-2.5/ltc1726-5 micropower triple supply monitor for 2.5v/5v, 3.3v and adj adjustable reset and watchdog timeouts ltc1727/ltc1728 micropower triple supply monitor with open-drain reset individual monitor outputs in msop/5-lead sot-23 ltc1985-1.8 micropower triple supply monitor with push-pull reset output 5-lead sot-23 package ltc2909 precision, triple/dual input uv, ov and negative voltage monitor 8-lead sot-23 and dfn packages ltc2912/ltc2913/ ltc2914 single/dual/quad uv and ov voltage monitors separate v cc pin, adjustable reset timer, h-grade temperature range ltc2915/ltc2916/ ltc2917/ltc2918 single voltage monitor with 27 unique thresholds manual reset, watchdog, tsot-8/msop-10 and 3mm w 2mm dfn packages, h-grade temperature range ltc2919 precision, triple/dual input uv, ov and negative voltage monitor 10-lead 3mm w 2mm and msop packages, h-grade temperature range (individual outputs for adj comparators and system rst) triple supply monitor with early power-fail warning (with manual reset and latchable reset for margining) + ltc2911-3 r2 76.8k r esd * 10k r1 100k r4 1.43m li-ion *optional resistor for added esd protection v trip = 3.37v v trip = 0.88v 3.3v 1.8v 1.0v r3 249k v1 v2 adj reset lobat rst pfo tmr vn2222 pfi c tmr 2.2nf 0.1f rst_latch signal high to perform margining 2911 ta07 gnd system logic dc/dc converter

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